Date Posted: August 24, 2016
Employment Type: Contract
Job Id: 7063
To perform professional technical work which is specific in nature and requires knowledge and application of basic engineering principles, theories and concepts to complete assignments under direct technical supervision. As an experienced Verification Engineer, you will creating a SystemVerilog/UVM testbench to simulate multiple FPGA designs. In this position you will review requirements, create test plans, architect and create a testbench, run simulations, collect coverage, track bugs, and run regressions. Many of the designs interact with Matlab/Simulink models. You are expected to understand the systems level design down to the individual FPGAs. You will be working with systems engineers, designers, and other verification engineers in a fast paced dynamic environment. Good communication skills and ability & desire to work as a team player are essential
Skills Required: Digital Verification Experience on FPGA/ASIC using using constrained random stimulus in a self-checking environment Strong understanding of System Verilog/UVM Ability to understand requirements Ability to work independently Bug tracking Version Control Tools. .
Skills Preferred: Linux Perl/Python Matlab/Simulink Make files GIT Mentor Graphics Questa.
Experience Required: Experience in building / creating a UVM environment
Experience in creating Test Benches from scratch
Experience with code coverage, functional coverage, regression testing,
Experience Preferred: Digital Signal Processing. PCIE
Education Required: Bachelor's degree in Engineering
MUST BE US CITIZEN – MUST BE WILLING TO UNDERGO SECURITY CLEARANCE INVESTIGATION